1. Field of the Invention
The present invention relates to a semiconductor device including a non-volatile memory cell, and to a method of manufacturing the same.
2. Description of the Related Art
FIG. 19 schematically shows the sectional structure of a conventional non-volatile memory cell in the channel width direction (i.e., a direction perpendicular to a direction channel current flows) (see JPN. PAT. APPLN KOKAI publication No. 2002-134634). In FIG. 19, reference numerals 81, 82, 83, 84, 85 and 86 denote silicon substrate, isolation film, tunnel insulating film, floating gate electrode, interelectrode insulating film, and control gate electrode, respectively.
The tunnel insulating film 83 has a nearly flat surface, and almost uniform in thickness except in the vicinity of the boundary with the isolation film 82. In other words, the tunnel insulating film 83 has a substantially same shape except the vicinity of the boundary with the isolation film 82.
In the vicinity of the boundary between the tunnel insulating film 83 and the isolation film 82, thickness of the tunnel insulating film 83 is thicker than other portions of the tunnel insulating film 83. The reason is that each surface of the silicon substrate 81 exposed on the sidewall of isolation trench and the floating gate electrode 84 is oxidized by thermal oxidation process conducted before the isolation trench is filled with the isolation film 82.
In the thermal oxidation process, the tunnel insulating film 83 is thicken in the region within about 5 nm inside from the boundary with the isolation film 82. In the write/erase operation tunnel current flows through almost whole the tunneling region as long as the film thickness increases to the degree described above. Namely, the tunnel current flows through the nearly entire region except in the vicinity of the boundary between the tunnel insulating film 83 and the isolation film 82.
The tunnel insulating film 63, in particular, the portion close to the vicinity of the boundary with the isolation film 82, receives so-called process damages more during manufacturing process than other portion. The process damages are metal contamination, halogen contamination, ion bombardment or charging damage. The process damages degrade the film quality of tunnel insulating film 83, in particular, the portion close to the vicinity of the boundary with the isolation film 82.
When the tunnel current flows through the tunnel insulating film 83, the degration of the film quality causes the following disadvantage. The generation of charge traps in the tunneling insulating film 83 or leakage current through the tunneling insulating film 83 remarkably increases near the boundary with the isolation film 82. The increase of the generation of charge traps or leakage current causes malfunction or reduction of charge storage capability due to the variations of threshold voltage in memory cells.
In the silicon substrate 81, the following regions are nearly the same (approximately entire regions of the tunnel insulating film 83 except in the vicinity of the boundary with the isolation film 82). One is a region through which tunnel current flows in the write/erase operation. Another is a region through which channel current flows in the cell transistor operation.
When the tunnel current flows through the tunnel insulating film 83, charge traps or interface states are generated in the tunnel insulating film 83. When charge traps or interface states are generated therein, the quality of the tunnel insulating film 83 deteriorates. The deterioration in the quality of the tunnel insulating film 83 is a factor of reducing the amount of channel current.